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?1 cxa1782cq/cr e95908c78 rf signal processing servo amplifier for cd players description the cxa1782cq/cr is a bipolar ic with built-in rf signal processing and various servo ics. a cd player servo can be configured by using this ic, dsp and driver. features low operating voltage (v cc ?v ee = 3.0 to 11.0v) low power consumption (39mw, v cc = 3.0v) supports pickup of either current output, voltage output automatic adjustment comparator for tracking balance gain single power supply and positive/negative dual power supplies applications rf i-v amplifier, rf amplifier focus and tracking error amplifier apc circuit mirror detection circuit defect detection and prevention circuits focus servo control tracking servo control sled servo control comparators of tracking adjustment for balance and gain structure bipolar silicon monolithic ic absolute maximum ratings (ta = 25?) supply voltage v cc 12 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? allowable power dissipation p d 833 (cxa1782cq) mw 457 (cxa1782cr) mw recommended operating condition operating supply voltage v cc ?v ee 3.0 to 11.0 v sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. cxa1782cq 48 pin qfp (plastic) cxa1782cr 48 pin lqfp (plastic)
?2 cxa1782cq/cr block diagram rf iv amp1 ?cs phase compensation ?racking phase compensation ? set ? il data register ?nput shift register ?dress.decoder ? set ?indow comp. 2 3 4 5 6 11 12 1 7 8 9 10 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 40 apc fe amp f iv amp te amp e iv amp rf iv amp2 bal1 bal2 bal3 tog1 tog2 tog3 level s fok mirr dfct i il ttl i il ttl i il ttl ?utput decoder tog1 to 3 bal1 to 3 fs1 to 4 tg1 to 2 tm1 to 7 ps1 to 4 lpf comp hpf comp tm6 tm5 tm4 tm3 tm7 tm2 tg1 tm1 dfct tzc comp fs4 dfct atsc fzc comp fs1 fs2 tg2 fe_bias f e ei v ee teo lpfi atsc tei tzc vc tdfct feo fei fgd flb fdfct fe_o srch fe_m tgu tg2 fset ta_m phd2 phd1 ld rf_m phd rf_o cp rf_i cb cc1 cc2 fok sens c.out xrst data xlt clk vcc sl_o iset sl_m ta_o sl_p the switch state in block diagram is for initial resetting. switch turns to side for 1 and to side for 0 in serial data truth table. dfct switch turns to side when defect signal generates for defect = e in serial data truth table. tg1 switch turns to side and tg2 switch is left open when tg1 and tg2 (address 1 : d3) is 1.
?3 cxa1782cq/cr pin description pin no. symbol i/o equivalent circuit description 1 feo o focus error amplifier output. connected internally to the fzc comparator input. 2 fei i 3 fdfct i focus error input. capacitor connection pin for defect time constant. 4 fgd i ground this pin through a capacitor when decreasing the focus servo high-frequency gain. 5 flb i external time constant setting pin for increasing the focus servo low- frequency. 6 fe_o o 13 ta_o o 16 sl_o o focus drive output. tracking drive output. sled drive output. 7 fe_m i focus amplifier inverted input. 147 50k 90k 7 250 6 13 16 40k 5 1 147 300 25p 174k 10k 51k 9k 147 100k 147 2 3 147 130k 4 68k 20
?4 cxa1782cq/cr pin no. symbol i/o equivalent circuit description 8 srch i external time constant setting pin for generating focus servo waveform. 9 tgu i external time constant setting pin for switching tracking high-frequency gain. 10 tg2 i external time constant setting pin for switching tracking high-frequency gain. 11 fset i high cut-off frequency setting pin for focus and tracking phase compensation amplifier. 12 ta_m i tracking amplifier inverted input. 14 sl_p i 15 sl_m i sled amplifier non-inverted input. sled amplifier inverted input. 14 147 12 147 100k 11 147k 11 15k 15k 147 50k 8 11 20k 9 110k 82k 2 10 470k 147 22 15
?5 cxa1782cq/cr pin no. symbol i/o equivalent circuit description 17 iset i setting pin for focus search, track jump, and sled kick current. 19 clk i 20 xlt i 21 data i 22 xrst i serial data transfer clock input from cpu. (no pull-up resistance) serial data input from cpu. (no pull-up resistance) reset input; resets at low. (no pull-up resistance) latch input from cpu. (no pull-up resistance) 23 c. out o 24 sens o track number count signal output. outputs fzc, dfct, tzc, gain, balance, and others according to the command from cpu. 25 fok o focus ok comparator output. 26 cc2 i 27 cc1 o 28 cb i input for the defect bottom hold output with capacitance coupled. defect bottom hold output. connection pin for defect bottom hold capacitor. 28 147 147 27 147 26 147 20k 100k 25 40k 17 147 147 19 20 21 22 15 1k 23 24 147 20k 100k
?6 cxa1782cq/cr pin no. symbol i/o equivalent circuit description 29 cp i connection pin for mirr hold capacitor. mirr comparator non-inverted input. 30 rf_i i 31 rf_o o 32 rf_m i 33 ld o apc amplifier output. 34 phd i apc amplifier input. 35 36 phd1 phd2 i i rf i-v amplifier inverted input. connect these pins to the photo diode a + c and b + d pins. 147 35 36 10k 11.6k 100 34 147 17 33 1k 10k 29 147 30 147 147 31 32 147 input for the rf summing amplifier output with capacitance coupled. rf sunning amplifier output. eye-pattern check point. rf summing amplifier inverted input. the rf amplifier gain is determined by the resistance connected between this pin and rfo pin.
?7 cxa1782cq/cr pin no. symbol i/o equivalent circuit description 37 fe_bias i bias adjustment of focus error amplifier. 38 39 f e i i f i-v and e i-v amplifier inverted input. connect these pins to photo diodes f and e. 40 ei i-v amplifier e gain adjustment. (when not using automatic balance adjustment) 42 teo o tracking error amplifier output. e-f signal is output. 43 lpfi i comparator input for balance adjustment. (input from teo through lpf) 147 43 147 23k 11k 4.8k 42 12k 10k 150k 150k 164k 32k 8 37 25p 147 260k 10 12p 38 39 513 40 260k 6.8k 20.3k 102k 57k 28k
?8 cxa1782cq/cr pin no. symbol i/o equivalent circuit description 44 tei i 47 tdfct i tracking error input. capacitor connection pin for defect time constant. 45 atsc i 46 tzc i 48 vc o window comparator input for atsc detection. tracking zero-cross comparator input. (v cc + v ee )/2 dc voltage output. 10k 46 75k 147 100k 147 44 47 45 10k 1k 100k 100k 1k 48 vc 50 120 120
?9 cxa1782cq/cr t1 t2 rf amplifier fe amplifier te amplifier t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 current consumption 1 current consumption 2 offset voltage gain max. output voltage-high max. output voltage-low offset voltage gain 1 voltage gain 1 voltage gain difference max. output voltage-high max. output voltage-low offset voltage gain f 0 voltage gain f 1 voltage gain f 2 voltage gain f 3 voltage gain e 0 voltage gain e 1 voltage gain e 2 1khz input ratio v1 = 100mv dc v1 = ?00mv dc v1 = 1khz i/o ratio v1 = 1khz i/o ratio v1 = 100mv dc v1 = 100mv dc v1 = 1khz tog1, 2, 3: off v1 = 1khz tog1: on reference to f 0 v1 = 1khz tog2: on reference to f 0 v1 = 1khz tog3: on reference to f 0 v1 = 1khz tog1, 2, 3: off v1 = 1khz bal1: on reference to e 0 v1 = 1khz bal2: on reference to e 0 o o o o o o o o o o o o o o o 18 41 31 42 10 14 20 ma ?0 ?4 ?0 ma ?0 0 50 25.1 28.1 31.1 mv ?.9 ?.3 v ?20 0 120 v 27.0 30.0 33.0 mv 27.0 30.0 33.0 db ?.0 0 3.0 db 1.0 1.3 db ?.3 ?.0 v ?5 0 25 v 0.5 3.5 6.5 mv ?.33 ?.83 ?.33 db ?.93 ?.43 ?.93 db ?.69 ?.19 ?.69 db ?.6 2.4 5.4 db 0.1 0.4 0.7 db 0.4 0.7 1.0 db item 1 2 3 4 5 6 8 7 9 10 11 12 13 14 15 16 17 18 measure- ment pin sd rst measurement conditions min. typ. max. unit sw conditions electrical characteristics (v cc = 1.5v, v ee = ?.5v, ta = 25?) 3f 3e 3d 3b 37 36 35 1.2 1.3 db db ratings 1
?10 cxa1782cq/cr te amplifier apc fcs servo trk servo v1 = 1khz bal3: on reference to e 0 v1 = 1v dc bal2: on v1 = 1v dc bal2: on v2 = 120mv v2 = 145mv v2 = 170mv 0.8ma sink t29 + t8 (or t9) output gain difference between sd = 00 and sd = 08. v1 = 200mv dc v1 = ?00mv dc pin 1 threshold (preliminary) t37 + t14 output gain difference between sd = 20 and sd = 25. v1 = ?.5v dc 1.08 0.5 ?00 ?00 ?80 ?00 ?00 18 49 1.0 ?40 360 185 12.25 16.1 1.0 1.38 0.6 ?.6 21.0 51 1.3 ?.3 ?00 500 225 14.6 18.1 1.3 1.68 ?.5 ?80 380 1120 500 100 24 53 ?5 ?.0 ?60 640 265 17.6 20.1 ?9 db v v mv mv mv mv mv db db db v v mv mv mv db db db v t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 t34 t35 t36 t37 t38 t39 t40 voltage gain e 3 max. output voltage-high max. output voltage-low output voltage 1 output voltage 2 output voltage 3 output voltage 4 center amplifier output offset dc voltage gain fcs total gain feed through max. output voltage-high max. output voltage-low search voltage (? search voltage (+) fzc threshold dc voltage gain trk total gain feed through max. output voltage-high o o o o o o o o o o o o o o o o o o o o 33 3f 3f 08 00 08 08 02 03 00 25 42 33 48 6 24 13 item 1 2 3 4 5 6 8 7 9 10 11 12 13 14 15 16 17 18 measure- ment pin sd measurement conditions min. typ. max. unit sw conditions ratings
13 10 24 25 16 23 24 ?11 cxa1782cq/cr trk servo sled mirr defect v1 = +0.5v dc output gain difference between sd = 20 and sd = 25. v1 = +0.4v dc v1 = ?.4v dc measures at c. out pin. measures at c. out pin. measures at c. out pin. measures at sens pin. measures at sens pin. measures at sens pin. measures at sens pin. ?40 360 ?5 7 ?0 12 120 ?00 50 1.0 ?50 450 30 1.8 2.5 1.8 ?.3 ?00 500 ?5 15 0 17 130 ?56 1.3 ?.3 ?00 600 ?.0 ?60 640 ? 25 20 22 140 ?30 ?4 ?.0 ?50 750 0.3 1 0.5 v mv mv mv mv mv mv mv mv db db v v mv mv khz vp-p vp-p khz khz vp-p vp-p t41 t42 t43 t44 t45 t46 t47 t48 t49 t50 t51 t52 t53 t54 t55 t56 t57 t58 t59 t60 t61 t62 max. output voltage-low jump output voltage (? jump output voltage (+) atsc threshold (? atsc threshold (+) tzc threshold bal comp threshold gain comp threshold fok threshold dc open gain feed through max. output voltage-high max. output voltage-low kick voltage (? kick voltage (+) max. operating frequency min. input operating voltage max. input operating voltage min. operating frequency max. operating frequency min. input operating voltage max. input operating voltage o o o o o o o o o o o o o o o o o o o o o o o o o o 25 2c 28 25 25 25 30 38 25 20 25 23 22 14 10 item 1 2 3 4 5 6 8 7 9 10 11 12 13 14 15 16 17 18 measure- ment pin sd measurement conditions min. typ. max. unit sw conditions ratings
?12 cxa1782cq/cr electrical characteristics measurement circuit 10k s10 0.1 47k 100k 200k 10k s11 s12 510k 0.015 200k 100k s13 10k s14 5.1k 13k 60k 240k v ee a vcc clk xlt data xrst vcc 10k vcc 10k 10k 3300p 1000p 3000p s15 10k 22k s16 vcc s17 v ee v2 s1 10k 10k s2 10k 390k s3 390k s4 a v ee s18 s5 s6 s7 s8 ac dc v1 0.1 s9 v 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 1 fe_bias f e ei v ee teo lpfi tei atsc tzc tdfct vc feo fei fdfct fgd flb fe_o fe_m srch tgu tg2 fset ta_m sens c. out xrst data xlt clk vcc iset sl_o sl_m sl_p ta_o pd2 pd1 pd ld rf_m rf_o rf_i cp cb cc1 cc2 fok
?13 cxa1782cq/cr application circuit (dual 5v power supplies) 0.1 680k 510k 0.015 vcc dsp dsp dsp micro computer 0.033 22k 2200p 0.1 0.1 100k 4.7 driver 0.033 vcc 100k driver 15k 22 3.3 driver 100k 8.2k 0.015 120k v ee dsp dsp micro computer 0.01 0.033 0.01 22k vcc 10 100/6.3v 1/6.3v 10h 100 500 v ee vcc v ee v ee 100k 150k 0.01 0.01 bpf 0.022 0.1 10 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 1 fe_bias f e ei v ee teo lpfi tei atsc tzc tdfct vc feo fei fdfct fgd flb fe o fe m srch tgu tg2 fset ta m sens c. out xrst data xlt clk vcc iset sl o sl m sl p ta o pd2 pd1 pd ld rf m rf o rf i cp cb cc1 cc2 fok 82k vcc 1k 1/0.3v a c b d 47k f e application circuit (single +3v power supply) 0.1 680k 510k 0.015 vcc dsp dsp dsp micro computer 0.033 22k 2200p 0.1 0.1 100k 4.7 driver 0.033 vcc 100k driver 15k 22 3.3 driver 100k 8.2k 0.015 120k dsp dsp micro computer 0.01 0.033 0.01 22k vcc 10 100/6.3v 1/6.3v 10h 100 500 vcc 1k 1/0.3v a c b d vcc 47k f e 100k 150k 0.01 0.01 bpf 0.022 0.1 10 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 1 fe_bias f e ei v ee teo lpfi tei atsc tzc tdfct vc feo fei fdfct fgd flb fe o fe m srch tgu tg2 fset ta m sens c. out xrst data xlt clk vcc iset sl o sl m sl p ta o pd2 pd1 pd ld rf m rf o rf i cp cb cc1 cc2 fok 10 vcc 82k application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
?14 cxa1782cq/cr description of functions rf amplifier the photo diode currents input to the input pins (pd1 and pd2) are each i-v converted via a 58k equivalent resistor by the pd i-v amplifiers. these signals are added by the rf summing amplifier, and the photo diode (a + b + c + d) current-voltage converted voltage is output to the rfo pin. an eye-pattern check can be performed at this pin. the low frequency component of the rfo output voltage is v rfo = 2.2 (v a + v b ) = 127.6k (ipd1 + ipd2). focus error amplifier the focus error amplifier calculates the difference between output va and vb of the rf i-v amplifier, and output current-voltage converted voltage of the photo diode (a + c ?b ?d). the feo output voltage (low frequency) is v feo = 5.4 (v a ?v b ) = (ipd2 ?ipd1) 315k . be aware that the rotation of the focus bias volume has reversed for the usual cd rf ic. 1k 3.3 a c b d 35 36 pd1 ipd1 ? pd2 ipd2 ? 58k va 10k vc pd1 iv amp 58k vb 10k vc pd2 iv amp 32 31 rf_m rf_o 22k vc rf summing amp ?(b + d) ?(a + c) vb va 32k 32k vc 25p 87k 164k 37 25p 174k fe amp 1 feo fe_bias 47k v ee v cc
?15 cxa1782cq/cr tracking error amplifier the photo diode currents input to e and f pins are each current-voltage converted by the e i-v and f i-v amplifiers. the cxa1782 tracking block has built-in circuits for balance and gain adjustments to enable software-based automatic adjustment. the balance adjustment is performed by varying the combined resistance value of the t-configured feedback resistance at e i-v amp. f i-v amp feedback resistance = r f1 + r f2 + = 403k e i-v amp feedback resistance = r e1 + r e2 + vary the value of r e3 in the formula above by using the balance adjustment switches (bal1 to bal3). for the gain adjustment, the te amp output is resistance-divided by the gain adjustment switches (tog1 to tog3), and it is output at pin 42. these balance and gain adjustment switches are controlled through software commands. 1k 3.3 ? if f 38 r f1 260k 12p vf f i-v amp 13k r f2 26k r f3 vc vc r e1 260k 12p ve e i-v amp vc ? ie 39 e 6.8k r e2 20.3k 102k bal1 57k bal2 28k bal3 vc 40 ei r e3 12k 10k 22k tog1 10k tog2 4.8k tog3 vc te amp 96k 30k 30k 96k vc 42 teo r e1 x r e2 r e3 r f1 x r f2 r f3
?16 cxa1782cq/cr tracking automatic adjustment for gain/balance balance adjustment this adjustment is performed by routing the tracking error signal (te signal) through the lpf, extracting the offset dc, and comparing it to the reference level. however, the te signal frequency distribution ranges form dc to 2khz. merely sending the signal through the lpf leaves lower frequency components, and the complete dc offset can not be extracted. to extract it, monitor the te signal frequency at all times, and perform adjustment only when, a frequency that can lower a sufficient gain appears on the lpf. use the c. out output to check this frequency. gain adjustment this adjustment is performed by passing the te signal through the hpf and comparing the ac component to the reference level. the hpf signal is implemented by taking the difference between the te signal and the lpf component input to pin 43. the comparison signal is output from pin 24 (sens). address 3 selects the automatic adjustment comparator output, and hpf for data (d3) = 1 or lpf for data (d3) = 0 is selected. the anti-shock circuit always operates in the cxa1782 so that tg1 and tg2 (address 1 : d3) should be set to 1 for tracking adjustment to prevent this effect. when the anti-shock function is not used, pin 45 (atsc) should be fixed to vc. 42 teo 100k 150k 0.01 0.01 lpf 43 + lpf hpf tzc dfct fzc 23 24 balance gain sens c. out balance ok gain ok frequency check resistance switching -con lpfi buffer amp the cxa1782 has balance control, gain control, and comparator circuits required to perform tracking automatic adjustment. lpf is set externally at approximately 100hz.
?17 cxa1782cq/cr center voltage generation circuit (single voltage application; connect to gnd when it? positive/negative dual power supplies.) maximum current is approximately 3ma. output impedance is approximately 50 . vcc 30k 30k 50 vc 48 vc v ee apc circuit when the laser diode is driven with constant current, the optical output possesses large negative temperature characteristics. therefore, the current must be controlled with the monitor photo diode to ensure the output remains constant. vcc 100/6.3v 10h 1/6.3v gnd ld pd v ee 34 33 ld pd 55k 10k v ee 56k 10k 10k 56k vcc 1k v ee vref 1.25v
?18 cxa1782cq/cr focus servo fzc 9k 51k fe 1 2 3 4 10k 2200p 22k feo fei 100k dfct fs4 focus phase compensation 68k 100k fe_o 6 focus coil 7 fe_m 100k 17 iset 120k 11 22 fs2 fs1 50k 50k 8 11 5 4.7 0.01 510k 0.1 fset flb 40k 0.47 0.1 680k fdfct fgd srch the above figure shows a block diagram of the focus servo. ordinarily the fe signal is input to the focus phase compensation circuit through a 68k resistance; however, when dfct is detected, the fe signal is switched to pass through a low-pass filter formed by the internal 100k resistance and the capacitance connected to pin 3. when this dfct prevention circuit is not used, leave pin 3 open. the defect switch operation can be enabled and disabled with command. the capacitor connected between pin 5 and gnd is a time constant to raise the low frequency in the normal playback state. the peak frequency of the focus phase compensation is approximately 1.2khz when a resistance of 510 is connected to pin 11. the focus search height is approximately 1.1vp-p when using the constants indicated in the above figure. this height is inversely proportional to the resistance connected between pin 17 and vee. however, changing this resistance also changes the height of the track jump and sled kick as well. the fzc comparator inverted input is set to 15% of v cc and vc (pin 48); (v cc ?vc) 15%. * 510k resistance is recommended for pin 11.
?19 cxa1782cq/cr tracking sled servo hpf 130mv + 17mv lpf te 42 teo 43 buffer amp lpfi 0.01 0.01 150k 100k 44 dfct tei 100k 47 tdfct 0.47 45 atsc 47p 330k 470k 0.047 0.022 46 tzc tzc 9 10 tgu tg2 0.033 470k tg2 20k 11 510k 0.01 fset tracking phase compensation 10k 90k tm4 tm3 11a 11a 12 13 100k tracking coil 82k 15k 22 3.3 14 15 sl_p tm2 tm6 tm5 22a 22a 100k 1k 1k 100k atsc 8.2k 120k 0.015 16 m sled motor sl_o sl_m tm1 680k 680k 66p ta_m ta_o tg1 tm7 the above figure shows a block diagram of the tracking and sled servo. the capacitor connected between pins 9 and 10 is a time constant to decrease the high-frequency gain when tg2 is off. the peak frequency of the tracking phase compensation is approximately 1.2khz when a 510k resistance connected to pin 11. in the cxa1782, tg1 and tg2 are inter-linked switches. to jump tracks in fwd and rev directions, turn tm3 or tm4 on. during this time, the peak voltage applied to the tracking coil is determined by the tm3 or tm4 current and the feedback resistance from pin 12. to be more specific, track jump peak voltage = tm3 (or tm4) current feedback resistance value the fwd and rev sled kick is performed by turning tm5 or tm6 on. during this time, the peak voltage applied to the sled motor is determined by the tm5 or tm6 current and the feedback resistance from pin 15; sled kick peak voltage = tm5 ( or tm6) current feedback resistance the values of the current for each switch are determined by the resistance connected between pin 17 and vee. when this resistance is 120k : tm3 ( or tm4) = 11a, and tm5 (or tm6) = 22a. as is the case with the fe signal, the te signal is switched to pass through a low-pass filter formed by the internal resistance (100k ) and the capacitance connected to pin 47.
?20 cxa1782cq/cr focus ok circuit 31 30 25 rf 15k 92k vg 54k 20k v cc 0.625v c5 0.01 rf_o rf_i fok 1 focus ok amp focus ok comparator the focus ok circuit creates the timing window okaying the focus servo from the focus search state. the hpf output is obtained at pin 30 from pin 31 (rf signal), and the lpf output (opposite phase) of the focus ok amplifier output is also obtained. the focus ok output reverses when v rfi ?v rfo ? ?.37v. note that, c5 determines the time constant of the hpf for the efm comparator and mirror circuit and the lpf of the focus ok amplifier. ordinarily, with a c5 equal to 0.01f selected, the fc is equal to 1khz, and block error rate degradation brought about by rf envelope defects caused by scratched discs can be prevented. defect circuit after the rfi signal is reverted, two time constants, long and short, are held at bottom. the short time constant bottom hold responds to 0.1ms or greater disc mirror defects, and the long time constant bottom hold holds the pre-defect mirror level. by differentiating and level-shifting these constants with capacitor coupling and comparing both signals, the mirror defect detection signal is generated. rf_o a 24 28 2 31 26 27 b defect amp cc1 cc2 sens cb 0.01 0.033 defect sw defect comparator defect bottom hold e c d e d c b a bottom hold (1) ; solid line: cc1 defect amp rfo defect bottom hold (2) ; dotted line: cc2 h l
?21 cxa1782cq/cr mirror circuit the mirror circuit performs peak and bottom hold after the rfi signal has been amplified. the peak and bottom holds are both held through the use of a time constant. for the peak hold, a time constant can follow a 30khz traverse, and, for the bottom hold, one can follow the rotation cycle envelope fluctuation. the dc playback envelope signal j is obtained by amplifying the difference between the peak and bottom hold signals h and i. signal j has a large time constant of 2/3 its peak value, and the mirror output is obtained by comparing it to the peak hold signal k. accordingly, when on the disc track, the mirror output is low; when between tracks (mirrored portion), it is high; and when a defect is detected, it is high. the mirror hold time constant must be sufficiently large compared with the traverse signal. in the cxa1782, this mirror output is used only during braking operations, and no external output pin is attached. accordingly, when connecting dsp such as the cxd2500 with mirr input pin, input the c. out output to the mirr input of the dsp. rf 20k 0.033 rf_o rf_i cp mirror comparator peak& bottom hold 31 30 1.4 29 k mirror hold amp j h i 1 logic g mirror amp rf_o h l 0v 0v 0v 0v g (rf_i) h (peak hold) i (bottom hold) (mirror hold) j k mirr
?22 cxa1782cq/cr commands the input data to operate this ic is configured as 8-bit data; however, below, this input data is represented by 2-digit hexadecimal numerals in the form $xx, where x is a hexadecimal numeral between 0 and f. commands for the cxa1782 can be broadly divided into four groups ranging in value from $0x to $3x. 1. $0x (?zc?at sens pin (pin 24)) these commands are related to focus servo control. the bit configuration is as shown below. d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 fs4 defect fs2 fs1 four focus-servo related switches exist: fs1, fs2, fs4, and defect corresponding to d0 to d3, respectively. $00 when fs1 = 0, pin 8 is charged to (22a ?11a) 50k = 0.55v. if, in addition, fs2 = 0, this voltage is no longer transferred, and the output at pin 6 becomes 0v. $02 from the state described above, the only fs2 becomes 1. when this occurs, a negative signal is output to pin 6. this voltage level is obtained by equation 1 below. (22a ?11a) 50k . . . . equation 1 $03 from the state described above, fs1 becomes 1, and a current source of +22a is split off. then, a cr charge/discharge circuit is formed, and the voltage at pin 8 decreases with the time as shown in fig. 1 below. this time constant is obtained with the 50k resistance and an external capacitor. by alternating the commands between $02 and $03, the focus search voltage can be constructed. (fig. 2) $04 when the fact that the rf signal is missing is detected and the scratches on the disc are detected with defect = 0, dfct (fs3) is turned on. 0v 0v $0002030203 0200 fig. 1. voltage at pin 8 when fs1 gose from 0 ? 1 fig. 2. constructing the search voltage by alternating between $02 and $03. (voltage at pin 6) resistance between pins 6 and 7 50k
?23 cxa1782cq/cr the instant the signal is brought into focus. $08 $03 ($00) $02 (20ms) (200ms) drive voltage focus error sens pin (fzc) focus ok 1-1. fs4 this switch is provided between the focus error input (pin 2) and the focus phase compensation, and is in charge of turning the focus servo on and off. $00 ? $08 focus off ? focus on 1-2. procedure of focus activation for description, suppose that the polarity is as described below. a) the lens is searching the disc from far to near; b) the output voltage (pin 6) is changing from negative to positive; and c) the focus s-curve is varying as shown below. the focus servo is activated at the operating point indicated by a in fig. 3. ordinarily, focus searching and the turning the focus servo switch on are performed during the focus s-curve transits the point a indicated in fig. 3. to prevent misoperation, this signal is anded with the focus ok signal. in this ic, fzc (focus zero cross) signal is output from the sens pin (pin 24) as the point a transit signal. in addition, focus ok is output as a signal indicating that the signal is in focus (can be in focus in this case). following the line of the above description, focusing can be well obtained by observing the following timing chart. * the broken lines in the figure indicate the voltage assuming the signal is not in focus. t a fig. 3. s-curve fig. 4. focus on timing chart
?24 cxa1782cq/cr 1-3. sens pin (pin 24) the output of the sens pin differs depending on the input data as shown below. $0x: fzc $1x: defect $2x: tzc $3x: automatic adjustment comparator output $4x to 7x: high-z 2. $1x (?efect?at sens pin (pin 24)) these commands deal with switching tg1/tg2, brake circuit on/off, and the sled kick output. the bit configuration is as follows d7 d6 d5 d4 d3 d2 d1 d0 0001 tg1, tg2 break sled kick circuit height on/off on/off tg1, tg2 the purpose of these switches is to switch the tracking servo gain up/normal. tg1 and tg2 are interlinked switches. the brake circuit (tm7) is to prevent the occurrence of such frequently occurring phenomena as extremely degraded actuator settling due to the servo motor exceeding the linear range causing what should be a 100-track jump to fall back down to a 10-track jump after a 100 or 10-track jump has been performed. to do this, when the actuator travels radially; that is, when it traverses from the inner track to the outer track of the disc and vice versa, the brake circuit utilizes the fact that the phase relationship between the rf envelope and the tracking error is 180?out-of-phase to cut the unneeded portion of the tracking error and apply braking. note that the time from the high to low transition of fzc to the time command $08 is asserted must be minimized. to do this, the software sequence shown in b is better than the sequence shown in a. fzc ? no yes f. ok ? no transfer $08 latch fzc ? no f. ok ? no transfer $08 latch (a) (b) yes yes yes fig. 5. poor and good software command sequences d1 (ps1) 0 0 1 1 d0 (ps0) 0 1 0 1 ? ? ? ? sled kick height relative value
?25 cxa1782cq/cr envelope detection waveform shaping waveform shaping edge detection 30 46 [ * b] [ * e] rf_i (tzc) tracking error cxa1782 (latch) q d ck (mirr) [ * c] [ * f] [ * g] brk d2 tm7 low: open high: make [ * a] [ * d] fig. 6. tmi movement during braking operation 0v (?irr? (?zc? braking is applied from here. [ * a] [ * b] [ * c] [ * d] [ * e] [ * f] [ * g] [ * h] from outer to inner track from inner to outer track fig. 7. internal waveform 3. $2x (?zc?at sens pin (pin 24)) these commands deal with turning the tracking servo and sled servo on/off, and creating the jump pulse and fast forward pulse during access operations. d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 0 tracking sled control control 00: off 00: off 01: servo on 01: servo on 10: f-jump 10: f-fast forward 11: r-jump 11: r-fast forward tm1, tm3, tm4 tm2, tm5, tm6
?26 cxa1782cq/cr 4. $3x these commands control the balance and gain control circuit switches used during automatic tracking adjustment. in the initial resetting state, bal1 to bal3 switches are off and tog1 to tog3 switches are on. balance adjustment the balance adjustment switches bal1 to bal3 can be controlled by setting d3 = 0. the switches are set using d0 to d2. at this time, the balance adjustment lpf comparator output is selected at the sens pin. data is set by specifying switch conditions d0 to d2 and sending a latch pulse with d3 = 0. sending a latch pulse with d3 = 1 does not change the balance switch settings. start c. out is the frequency high enough ? sens output balance ok ? adjustment completed bal1 to bal3 switch control yes no gain adjustment the gain adjustment switches tog1 to tog3 can be controlled by setting d3 = 1. these switches are set using d0 to d2. at this time, the balance adjustment hpf comparator output is selected for sens pin. in a fashion similar to the method used with the balance adjustment, set the data by sending a latch pulse with d3 = 1, specifying the switch conditions d0 to d2. start sens gain ok ? adjustment completed tog1 to tog3 switch control yes no balance adjustment gain adjustment
?27 cxa1782cq/cr cpu serial interface timing chart t wck d0 d1 d2 d3 d4 d5 d6 d7 d0 t wck t su 1/fck t h t cd t wl t d data clk xlt item clock frequency clock pulse width setup time hold time delay time latch pulse width data transfer interval symbol fck fwck t su t h t d t wl t cd min. 500 500 500 500 1000 1000 type. max. unit mhz ns ns ns ns ns ns 1 (v cc = 3.0v) system control focus control tracking control tracking mode select d7 d6 d5 d4 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 fs4 focus on = 1, off = 0 tg1, tg2 on = 1, off = 0 defect (fs3) disable = 1 enable = 0 brake on = 1, off = 0 fs2 search on = 1, off = 0 sled kick + 2 fs1 search up = 1, down = 0 sled kick + 1 fzc defect tzc gain/bal tracking mode * 1 sled mode * 2 automatic tracking adjustment mode adress d3 d2 d1 d0 data sens output * 1 tracking mode fwd jump rev jump d3 0 0 1 1 d2 0 1 0 1 off on * 2 sled mode fwd move rev move d1 0 0 1 1 d0 0 1 0 1 off on item
?28 cxa1782cq/cr serial data truth table focus control hex functions fs = 4321 fs4 defect fs2 fs1 $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0a $0b $0c $0d $0e $0f serial data 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0e0 0 0e0 1 0e1 0 0e1 1 0d0 0 0d0 1 0d1 0 0d1 1 1e0 0 1e0 1 1e1 0 1e1 1 1d0 0 1d0 1 1d1 0 1d1 1 defect e: enable d: disable tracking mode tm = 6 5 4 3 2 1 hex $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2a $2b $2c $2d $2e $2f 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 0 0 1 0 0 1 1 1 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 0 1 1 0 0 0 0 1 0 1 1 0 1 0 0 1 0 1 1 1 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 1 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 0 1 0 0 0
?29 cxa1782cq/cr automatic adjustment mode tog sw 3 2 1 bal sw 3 2 1 hex $30 $31 $32 $33 $34 $35 $36 $37 $38 $39 $3a $3b $3c $3d $3e $3f 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 1 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 1 0 0 1 1 1 0 1 0 0 0 1 1 1 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? data d3 = 0: balance switch setting data d3 = 1: gain switch setting note) 0 means off and 1 means on for tog sw and bal sw. these are not equal to the setting values of each bit for serial data. initial state (resetting state) item focus control tracking control tracking mode select d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 address data hexadecimal 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 $00 $10 $20 $37 $38 the above data means the following operation modes. focus control focus off, defect enable, focus search off, focus search down tracking control tg1 ?tg2 off, brake off, sled kick + 2 off, sled kick + 1 off tracking mode tracking off, sled off select tracking gain ? min. (tog sw: 1 1 1) tracking balance: re3 ? max. (tbal sw: 0 0 0)
?30 cxa1782cq/cr 6. sled amplifier the sled amplifier may oscillate when used by the buffer amplifier. use with a gain of approximately 20db. sled/tracking internal phase compensation and reference design material notes on operation 1. fset pin the fset pin determines the fc for the focus and tracking high-frequency phase compensation. 2. iset pin iset current = 1.27v/r = focus search current = tracking jump current = sled kick current ($1x: ps1 = ps0 = 0) use the setting resistance within the range of 120k to 240k . if the resistance value is out of this range, the oscillation may be occurred in the iset block. 3. fe (focus error)/te (tracking error) gain changing method 1) high gain: resistance between fe pins (pins 6 and 7) 100k ? large resistance between te pins (pins 12 and 13) 100k ? large 2) low gain: a signal, whose resistance is divided between pins 1 and 2, is input to fe. the internal gain adjustment circuit is used for te. 4. input voltage at pins 19 to 22 of the microcomputer interface should be as follows: v ih v cc 90% or more v il v cc 10% or less 5. focus ok circuit 1) refer to the ?escription of operation?for the time constant setting of the focus ok amplifier lpf and the mirror amplifier hpf. v cc 20k 40k 100k v ee v ee 25 r l fok v cc the fok and comparator output are as follows: output voltage high: v fokh ? near v cc output voltage low: v fokl ? vsat (npn) item sd measurement pin conditions typ. unit 1.2khz gain 1.2khz phase 1.2khz gain 1.2khz phase 2.7khz gain 2.7khz phase 08 08 25 25 25 ? 13 25 ? 13 6 c flb = 0.1f c fgd = 0.1f 21.5 63 13 ?25 26.5 ?30 db deg db deg db deg c tgu = 0.1f 13 fcs trk 1 2
?31 cxa1782cq/cr package outline unit: mm cxa1782cq sony code eiaj code jedec code m package structure package material lead treatment lead material package weight epoxy resin solder / palladium plating copper / 42 alloy 48pin qfp (plastic) 15.3 0.4 12.0 ?0.1 + 0.4 0.8 0.3 ?0.1 + 0.15 0.12 13 24 25 36 37 48 112 2.2 ?0.15 + 0.35 0.9 0.2 0.1 ?0.1 + 0.2 13.5 0.15 0.15 ?0.05 + 0.1 qfp-48p-l04 * qfp048-p-1212-b 0.7g cxa1782cr sony code eiaj code jedec code package material lead treatment lead material package weight epoxy / phenol resin solder plating 42 alloy package structure 48pin lqfp (plastic) 9.0 0.2 * 7.0 0.1 1 12 13 24 25 36 37 48 (0.22) 0.18 ?0.03 + 0.08 0.5 0.08 (8.0) 0.5 0.2 0.127 ?0.02 + 0.05 0.1 0.1 0.5 0.2 a 1.5 ?0.1 + 0.2 0?to 10 detail a 0.2g lqfp-48p-l01 * qfp048-p-0707-a 0.1 note: dimension * ?does not include mold protrusion. note : palladium plating this product uses s-pdppf (sony spec.-palladium pre-plated lead frame). note : palladium plating this product uses s-pdppf (sony spec.-palladium pre-plated lead frame).

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